# Configuration file for the Intel Xeon X7560 Beckton

#include nehalem

[perf_model/core]
frequency = 2.266

[perf_model/l3_cache]
perfect = false
cache_block_size = 64
cache_size = 24576 # 24 MiB
associativity = 16
address_hash = mask
replacement_policy = lru
data_access_time = 30
tags_access_time = 10
####TODO####writeback_time = 390
perf_model_type = parallel
writethrough = 0
shared_cores = 8

[perf_model/dram_directory]
# Intel 7300 Northbridge Specs: http://www.intel.com/Products/Server/Chipsets/7300/7300-overview.htm
# 7300 tracks 1,048,576 caches lines, in a 16-way configuration.
# total_entries = number of entries per directory controller.
total_entries = 1048576 # Intel 7300 Northbridge Specs: http://www.intel.com/Products/Server/Chipsets/7300/7300-overview.htm
associativity = 16
directory_type = full_map

[perf_model/dram]
# Currently set to -1, which means that we have a number of distributed DRAM controllers (4 in this case)
# By setting the num_controllers to 1, we will simulate the number of DRAM controllers more accurately
# Nevertheless, this could reduce the DRAM bandwidth below what the level is for the 7300 Northbridge.
num_controllers = -1
controllers_interleaving = 8
# DRAM access latency in nanoseconds. Should not include L1-LLC tag access time, directory access time (24 cycles = 9 ns),
# or network time [(cache line size + 2*{overhead=40}) / network bandwidth = 18 ns]
latency = 173

[network]
memory_model_1 = bus
memory_model_2 = bus

[network/bus]
# Dunnington Specs: http://www.intel.com/assets/PDF/datasheet/320335.pdf
#  1066 MTS
#  64-bit bus
#  Max per-cpu BW = 8.528 GB/s (not GiB/s)
# Intel 7300 Chipset Overview: http://www.intel.com/products/server/chipsets/7300/7300-overview.htm
#  PtP (CPU to chipset) Directory-based cache coherency
# Intel 7300 Chipset Details: http://www.intel.com/products/server/chipsets/7300/7300-technicaldocuments.htm
bandwidth = 8 # in GB/s
